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km48s8020b cmos sdram rev .7 july 1998 revision history revision .3(november 1997) - t rdl has changed 10ns to 12ns. - binning -10 does not meet pc100 characteristics . so ac parameter/characteristics have changed to 64m 2nd values. revision .4 (february 1998) - input leakage currents (inputs / dq) are changed. iil(inputs) : 5ua to 1ua, i il (dq) : 5ua to 1.5ua. - the measuring condition of tr/tf is clearly defined each as 0pf +50 w to v ss /v dd , 50pf +50 w to v ss /v dd - cin to be measured at v dd = 3.3v, ta = 23 c, f = 1mhz, v ref =1.4v 200 mv. - ac operating condition is changed as defined : vih(max) = 5.6v ac. the overshoot voltage duration is 3ns. vil(min) = -2.0v ac. the undershoot voltage duration is 3ns. - icc3ps is changed 1ma to 2ma. - icc6 for low power is changed 400ua to 450ua. revision .5 (march 1998) - i cc2 n, i cc2 ns, i cc3 n & i cc3 ns values are changed. revision .6 (june 1998) - t sh (-10 binning) is revised. revision .7 (july 1998) - simplified truth table is revised.
km48s8020b cmos sdram rev .7 july 1998 the km48s8020b is 67,108,864 bits synchronous high data rate dynamic ram organized as 2 x 4,194,304 words by 8 bits, fabricated with samsung s high performance cmos technol- ogy. synchronous design allows precise cycle control with the use of system clock i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance mem- ory system applications. ? jedec standard 3.3v power supply ? lvttl compatible with multiplexed address ? dual banks operation ? mrs cycle with address key programs -. cas latency (2 & 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock ? burst read single-bit write operation ? dqm for masking ? auto & self refresh ? 64ms refresh period (4k cycle) general description features functional block diagram 4m x 8bit x 2 banks synchronous dram ordering information part no. max freq. interface package km48s8020bt-g/f8 125mhz lvttl 54 tsop(ii) km48s8020bt-g/fh 100mhz km48s8020bt-g/fl 100mhz km48s8020bt-g/f10 100mhz samsung electronics reserves the right to change products or specification without notice. * bank select data input register 4m x 8 s e n s e a m p o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r e f r e s h c o u n t e r r o w d e c o d e r c o l . b u f f e r l r a s l c b r lcke lras lcbr lwe ldqm clk cke cs ras cas we dqm lwe ldqm dqi clk add lcas lwcbr 4m x 8 timing register
km48s8020b cmos sdram rev .7 july 1998 v dd dq0 v ddq n.c dq1 v ssq n.c dq2 v ddq n.c dq3 v ssq n.c v dd n.c we cas ras cs ba a12 a10/ap a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 pin configuration (top view) v ss dq7 v ssq n.c dq6 v ddq n.c dq5 v ssq n.c dq4 v ddq n.c v ss n.c/rfu dqm clk cke n.c a11 a9 a8 a7 a6 a5 a4 v ss 54pin tsop (ii) (400mil x 875mil) (0.8 mm pin pitch) pin function description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a 0 ~ a 12 address row/column addresses are multiplexed on the same pins. row address : ra 0 ~ ra 12 , column address : ca 0 ~ ca 8 ba bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. dqm data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. dq 0 ~ 7 data input/output data inputs/outputs are multiplexed on the same pins. v dd /v ss power supply/ground power and ground for the input buffers and the core logic. v ddq /v ssq data output power/ground isolated power supply and ground for the output buffers to provide improved noise immunity. n.c/rfu no connection /reserved for future use this pin is recommended to be left no connection on the device.
km48s8020b cmos sdram rev .7 july 1998 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1 w short circuit current i os 50 ma permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note supply voltage v dd , v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v ddq +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current (inputs) i il -1 - 1 ua 3 input leakage current (i/o pins) i il -1.5 - 1.5 ua 3,4 capacitance (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref = 1.4v 200 mv) pin symbol min max unit clock c clk 2.5 4.0 pf ras , cas , we , cs , cke, dqm c in 2.5 5.0 pf address c add 2.5 5.0 pf dq 0 ~ dq 7 c out 4.0 6.5 pf 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v v out v ddq. notes :
km48s8020b cmos sdram rev .7 july 1998 1. measured with outputs open. 2. refresh period is 64ms. 3. km48s8020bt-g** 4. km48s8020bt-f** notes : dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition cas latency version unit note -8 -h -l -10 operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i ol = 0 ma 105 95 95 90 ma 1 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 15ns 1 ma i cc2 ps cke & clk v il (max), t cc = 1 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 20 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 10 active standby current in power-down mode i cc3 p cke v il (max), t cc = 15ns 2 ma i cc3 ps cke & clk v il (max), t cc = 2 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 30 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 20 ma operating current (burst mode) i cc4 i ol = 0 ma page burst 2banks activated t ccd = 2clks 3 125 105 105 105 ma 1 2 95 105 95 90 refresh current i cc5 t rc 3 t rc (min) 150 135 ma 2 self refresh current i cc6 cke 0.2v 1 ma 3 450 ua 4
km48s8020b cmos sdram rev .7 july 1998 ac operating test conditions (v dd = 3.3v 0.3v , t a = 0 to 70 c) parameter value unit input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 3.3v 1200 w 870 w output 50pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50 w output 50pf z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit operating ac parameter (ac operating conditions unless otherwise noted) parameter symbol version unit note -8 -h -l -10 row active to row active delay t rrd (min) 16 20 20 20 ns 1 ras to cas delay t rcd (min) 20 20 20 24 ns 1 row precharge time t rp (min) 20 20 20 24 ns 1 row active time t ras (min) 48 50 50 50 ns 1 t ras (max) 100 us row cycle time t rc (min) 68 70 70 80 ns 1 last data in to row precharge t rdl (min) 8 10 10 12 ns 2 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 number of valid output data cas latency=3 2 ea 4 cas latency=2 1 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. notes :
km48s8020b cmos sdram rev .7 july 1998 ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -8 -h -l -10 unit note min max min max min max min max clk cycle time cas latency=3 t cc 8 1000 10 1000 10 1000 10 1000 ns 1 cas latency=2 12 10 12 13 clk to valid output delay cas latency=3 t sac 6 6 6 7 ns 1,2 cas latency=2 6 6 7 7 output data hold time cas latency=3 t oh 3 3 3 3 ns 2 cas latency=2 3 3 3 3 clk high pulse width t ch 3 3 3 3.5 ns 3 clk low pulse width t cl 3 3 3 3.5 ns 3 input setup time t ss 2 2 2 2.5 ns 3 input hold time t sh 1 1 1 1 ns 3 clk to output in low-z t slz 1 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 6 6 6 7 ns cas latency=2 6 6 7 7 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. notes : dq buffer output drive characteristics parameter symbol condition min typ max unit notes output rise time trh measure in linear region : 1.2v ~1.8v 1.37 4.37 volts/ns 4 output fall time tfh measure in linear region : 1.2v ~1.8v 1.30 3.8 volts/ns 4 output rise time trh measure in linear region : 1.2v ~1.8v 2.8 3.9 5.6 volts/ns 1,2,3 output fall time tfh measure in linear region : 1.2v ~1.8v 2.0 2.9 5.0 volts/ns 1,2,3 1. output rise and fall time must be guaranteed across v dd and process range. 2. rise time specification based on 0pf + 50 ohms to v ss , use these values to design to. 3. fall time specification based on 0pf + 50 ohms to v dd , use these values to design to. 4. measured into 50pf only, use these values to characterize to. 5. all measurements done with respect to v ss . notes :
km48s8020b cmos sdram rev .7 july 1998 i oh characteristics (pull-up) voltage 100mhz min 100mhz max 66mhz min (v) i (ma) i (ma) i (ma) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 -0.7 2.6 -21.1 -129.2 -7.5 2.4 -34.1 -153.3 -13.3 2.0 -58.7 -197.0 -27.5 1.8 -67.3 -226.2 -35.5 1.65 -73.0 -248.0 -41.1 1.5 -77.9 -269.7 -47.9 1.4 -80.8 -284.3 -52.4 1.0 -88.6 -344.5 -72.5 0.0 -93.0 -502.4 -93.0 ibis specification i ol characteristics (pull-down) voltage 100mhz min 100mhz max 66mhz min (v) i (ma) i (ma) i (ma) 0.0 0.0 0.0 0.0 0.4 27.5 70.2 17.7 0.65 41.8 107.5 26.9 0.85 51.6 133.8 33.3 1.0 58.0 151.2 37.6 1.4 70.7 187.7 46.6 1.5 72.9 194.4 48.0 1.65 75.4 202.5 49.5 1.8 77.0 208.6 50.7 1.95 77.6 212.0 51.5 3.0 80.3 219.6 54.2 3.45 81.4 222.6 54.9 0 -100 -200 -300 -400 -500 -600 0 3 0.5 1 1.5 2 2.5 3.5 voltage m a 250 200 150 100 50 0 0 3 0.5 1 1.5 2 2.5 3.5 voltage m a 66mhz and 100mhz pull-up 66mhz and 100mhz pull-down i oh min (100mhz) i oh max (66 and 100mhz) i oh min (66mhz) i ol min (100mhz) i ol max (100mhz) i ol min (66mhz)
km48s8020b cmos sdram rev .7 july 1998 v dd clamp @ clk, cke, cs , dqm & dq v dd (v) i (ma) 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 v ss clamp @ clk, cke, cs , dqm & dq v ss (v) i (ma) -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 20 15 10 5 0 0 3 1 2 voltage m a i (ma) voltage m a i (ma) minimum v dd clamp current (referenced to v dd ) minimum v ss clamp current 0 -10 -20 -30 -40 -3 0 -2 -1 -50 -60
km48s8020b cmos sdram rev .7 july 1998 frequency vs. ac parameter relationship table km48s8020bt-8 frequency cas latency t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 68ns 48ns 20ns 16ns 20ns 8ns 8ns 8ns 125mhz (8.0ns) 3 9 6 3 2 3 1 1 1 100mhz (10.0ns) 3 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 4 2 2 2 1 1 1 75mhz (13.0ns) 2 6 4 2 2 2 1 1 1 66mhz (15.0ns) 2 5 4 2 2 2 1 1 1 (unit : number of clock) km48s8020bt-l frequency cas latency t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100mhz (10.0ns) 3 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 5 2 2 2 1 1 1 75mhz (13.0ns) 2 6 4 2 2 2 1 1 1 66mhz (15.0ns) 2 5 4 2 2 2 1 1 1 60mhz (16.7ns) 2 5 3 2 2 2 1 1 1 (unit : number of clock) km48s8020bt-h frequency cas latency t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns 100mhz (10.0ns) 2 7 5 2 2 2 1 1 1 83mhz (12.0ns) 2 6 5 2 2 2 1 1 1 75mhz (13.0ns) 2 6 4 2 2 2 1 1 1 66mhz (15.0ns) 2 5 4 2 2 2 1 1 1 60mhz (16.7ns) 2 5 3 2 2 2 1 1 1 (unit : number of clock) km48s8020bt-10 frequency cas latency t rc t ras t rp t rrd t rcd t ccd t cdl t rdl 80ns 50ns 24ns 20ns 24ns 10ns 10ns 12ns 100mhz (10.0ns) 3 8 5 3 2 3 1 1 2 83mhz (12.0ns) 3 7 5 2 2 2 1 1 1 75mhz (13.0ns) 2 7 4 2 2 2 1 1 1 66mhz (15.0ns) 2 6 4 2 2 2 1 1 1 60mhz (16.7ns) 2 5 3 2 2 2 1 1 1 (unit : number of clock)
km48s8020b cmos sdram rev .7 july 1998 simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba a 10 /ap a 12 ~ a 11 a 9 ~ a 0 note register mode register set h x l l l l x op code 1,2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~ a 8 ) 4 auto precharge enable h 4,5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~ a 8 ) 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h v x 7 no operation command h x h x x x x x l h h h 1. op code : operand code a 0 ~ a 12 & ba : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba : bank select addresses. if "low" at read, write, row active and precharge, bank a is selected. if "high" at read, write, row active and precharge, bank b is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2) notes : x

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